HD6432633 Datasheet, PDF (903/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Table 18-6 I²C Bus Timing (SCL and SDA Output)
Item
Symbol
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
t _SCLO
t _SCLHO
t _SCLLO
t _BUFO
t _STAHO
t _STASO
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
t _STOSO
t _SDASO
Data output hold time
t _SDAHO
Note: * 6t_cyc when IICX is 0, 12t_cyc when 1.
Output Timing
28t_cyc to 256t_cyc
0.5t_SCLO
0.5t_SCLO
0.5t_SCLO – 1t_cyc
0.5t_SCLO – 1t_cyc
1t _SCLO
0.5t_SCLO + 2t_cyc
1t_SCLLO – 3t_cyc
1t_SCLL – 3t_cyc
3t _cyc
Unit Notes
ns
Figure 25-33,
ns
figure 26-33
ns
(reference)
ns
ns
ns
ns
ns
ns
• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t_cyc, as shown in tables 25-10 and 26-10 in section
25 and 26, Electrical Characteristics. Note that the I²C bus interface AC timing specifications
will not be met with a system clock frequency of less than 5 MHz.
• The I²C bus interface specification for the SCL rise time t_sr is under 1000 ns (300 ns for high-
speed mode). In master mode, the I²C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t_sr (the time for SCL to go from low to V_IH) exceeds
the time determined by the input clock of the I²C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
18-7.
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