HD6432633 Datasheet, PDF (732/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

WDT0 TCSR Bit 3—Reserved Bit: This bit is always read as 1 and cannot be modified.
WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal
reset request and an NMI request when the TCNT overflows during the watchdog timer mode.
Bit 3
RTS/NMI
0
1
Description
NMI request.
Internal reset request.
(Initial value)
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (ø) or subclock (ø SUB), for input to TCNT.
Note: In the case of the H8S/2695, only 0 should be written to the RST/NMI bit in the TCSR1
register.
WDT0 Input Clock Select
Description
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Clock
Overflow Period* (where ø = 25 MHz)
0
0
0
ø/2 (Initial value) 20.4 µs
1
ø/64
655.3 µs
1
0
ø/128
1.3 ms
1
ø/512
5.2 ms
1
0
0
ø/2048
20.9 ms
1
ø/8192
83.8 ms
1
0
ø/32768
335.5 ms
1
ø/131072
1.34 s
Note: * An overflow period is the time interval between the start of counting up from H'00 on the
TCNT and the occurrence of a TCNT overflow.
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