HD6432633 Datasheet, PDF (853/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Section 18 I²C Bus Interface [Option]
(This function is not available in the H8S/2695)
A two-channel I²C bus interface is available as an option in the H8S/2633 Series. The I²C bus
interface is not available for the H8S/2633 Series. Observe the following notes when using this
option.
1. For mask-ROM versions, a W is added to the part number in products in which this optional
function is used.
Examples: HD6432633WF
2. The product number is identical for F-ZTAT versions. However, be sure to inform your
Hitachi sales representative if you will be using this option.
18.1 Overview
A two-channel I²C bus interface is available for the H8S/2633 Series as an option. The I²C bus
interface conforms to and provides a subset of the Philips I²C bus (inter-IC bus) interface
functions. The register configuration that controls the I²C bus differs partly from the Philips
configuration, however.
Each I²C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer
data, saving board and connector space.
18.1.1 Features
• Selection of addressing format or non-addressing format
 I²C bus format: addressing format with acknowledge bit, for master/slave operation
 Serial format: non-addressing format without acknowledge bit, for master operation only
• Conforms to Philips I²C bus interface (I²C bus format)
• Two ways of setting slave address (I²C bus format)
• Start and stop conditions generated automatically in master mode (I²C bus format)
• Selection of acknowledge output levels when receiving (I²C bus format)
• Automatic loading of acknowledge bit when transmitting (I²C bus format)
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