HD6432633 Datasheet, PDF (1313/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

TSTR—Timer Start Register
H'FEB0
TPU Common
Bit
:7
—
Initial value : ₀
R/W
:—
6
5
4
3
2
1
0
—
CST5 CST4 CST3 CST2 CST1 CST0
0
0
0
0
0
0
0
—
R/W R/W R/W R/W R/W R/W
Counter start 5 to 0
0
TCNTn counting operation disabled.
1
TCNTn counting operation enabled.
(n= 5 to 0)
Note: When the TIOC pin is operating as an output pin, writing 0 to a CST bit
disables counting. The TIOC pins output compare output level is maintained.
When a CST bit is 0, the output level of the pin is updated to the set initial
output value by writing to TIOR.
TSYR—Timer Synchro Register
H'FEB1
TPU Common
Bit
:7
—
Initial value : 0
R/W
:—
6
5
4
3
2
1
0
— SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
0
0
0
0
0
0
0
—
R/W
R/W
R/W
R/W
R/W
R/W
Timer sync 5 to 0
0
TCNTn operate independently (TCNTs are preset and cleared
independently of other channels)
1
TCNTn operate in sync mode. Synchronized
TCNT presetting and clearing enabled.
Notes: 1.
2.
(n= 5 to 0)
The SYNC bit of a minimum of two channels must be set to 1 in order to
select sync operation.
To enable sync clearing, in addition to the SYNC bits, the TCR CCLR2 to
CCLR0 bits must be set for the TCNT clearing factors.
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