HD6432633 Datasheet, PDF (650/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
data prior to the write.
Figure 11-52 shows the timing in this case.
ø
Address
Write signal
Compare
match signal
Buffer
register
TGR
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N
M
N
Figure 11-52 Contention between Buffer Register Write and Compare Match
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