HD6432633 Datasheet, PDF (273/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.5.11 Refresh Control
This LSI has a DRAM refresh control function. There are two refresh methods: (1) CAS-before-
RAS (CBR) and (2), self refresh.
(1) CAS-Before-RAS (CBR) Refresh
To select CBR refresh, set the RFSHE bit of DRAMCR to 1 and clear the RMODE bit to 0.
In CBR refresh, the input clock selected with the CKS2 to CKS0 bits of DRAMCR are used for
the RTCNT count-up. Refresh control is performed when the count reaches the value set in
RTCOR (compare match). The RTCNT is then reset and the count again started from H'00. That
is, the refresh is repeated at the set interval determined by RTCOR and CKS2 to CKS0. Set
RTCOR and CKS2 to CKS0 to satisfy the refresh cycle for the DRAM being used.
The RTCNT count up starts when the CKS2 to CKS0 bits are set. The RTCNT and RTCOR
values should therefore be set before setting CKS2 to CKS0. When a value is set in RTCOR,
RTCNT is cleared. When RTCNT is set at the same time that it is reset by a compare match, the
value written to RTCNT takes precedence.
When performing refresh control (RFSHE=1), do not clear the CMF flag.
Figure 7-25 shows RTCNT operation. Figure 7-26 shows compare match timing. And figure 7-27
show CBR refresh timing.
Some types of DRAM do not allow the WE signal to be changed during the refresh cycle. In this
case, set CBRM to 1. Figure 7-28 shows the timing. The CS signal is not controlled and a Low
level is output when an access request occurs.
Note that other normal spaces are accessed during the CBR refresh cycle.
RTCOR
RTCNT
H'00
Refresh request
Figure 7-25 RTCNT Operation
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