HD6432633 Datasheet, PDF (213/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

6.3 Operation
The operation flow from break condition setting to PC break interrupt exception handling is shown
in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt Due
to Data Access, taking the example of channel A.
6.3.1 PC Break Interrupt Due to Instruction Fetch
(1) Initial settings
 Set the break address in BARA. For a PC break caused by an instruction fetch, set the
address of the first instruction byte as the break address.
 Set the break conditions in BCRA.
BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must
be the CPU. Set 0 to select the CPU.
BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.
BCRA bits 2–1 (CSELA1–0): Set 00 to specify an instruction fetch as the break condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
(2) Satisfaction of break condition
 When the instruction at the set address is fetched, a PC break request is generated
immediately before execution of the fetched instruction, and the condition match flag
(CMFA) is set.
(3) Interrupt handling
 After priority determination by the interrupt controller, PC break interrupt exception
handling is started.
6.3.2 PC Break Interrupt Due to Data Access
(1) Initial settings
 Set the break address in BARA. For a PC break caused by a data access, set the target
ROM, RAM, I/O, or external address space address as the break address. Stack operations
and branch address reads are included in data accesses.
 Set the break conditions in BCRA.
BCRA bit 6 (CDA): Select the bus master.
BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.
BCRA bits 2–1 (CSELA1–0): Set 01, 10, or 11 to specify data access as the break
condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
159