HD6432633 Datasheet, PDF (343/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

8.5.6 Normal Mode
In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA
to 0.
In normal mode, MAR is updated after each byte or word transfer in response to a single transfer
request, and this is executed the number of times specified in ETCRA. The transfer source is
specified by MARA, and the transfer destination by MARB.
Table 8-10 summarizes register functions in normal mode.
Table 8-10 Register Functions in Normal Mode
Register
23
MARA
Function
0 Source address
register
Initial Setting
Start address of
transfer source
Operation
Incremented/decremented
every transfer, or fixed
23
MARB
0 Destination
Start address of Incremented/decremented
address register transfer destination every transfer, or fixed
15
0 Transfer counter Number of transfers Decremented every
ETCRA
transfer; transfer ends
when count reaches
H'0000
Legend
MARA : Memory address register A
MARB : Memory address register B
ETCRA : Transfer count register A
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed.
Incrementing, decrementing, or holding a fixed value can be set separately for MARA and
MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a
transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
289