HD6432633 Datasheet, PDF (882/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
SLA R/W A
DATA
A
DATA
A/A
P
Figure 18-5 I²C Bus Timing
Table 18-4 I²C Bus Data Format Symbols
Legend
S
SLA
R/W
A
DATA
P
Start condition. The master device drives SDA from high to low while SCL is high
Slave address, by which the master device selects a slave device
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
Acknowledge. The receiving device (the slave in master transmit mode, or the master
in master receive mode) drives SDA low to acknowledge a transfer
Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or
LSB-first format is selected by bit MLS in ICMR
Stop condition. The master device drives SDA from low to high while SCL is high
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