HD6432633 Datasheet, PDF (278/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.6.2 DDS=0
When the DRAM space is accessed in DMAC single address mode, always perform full access
(normal access). The DACK output level changes to Low afer the T_r state in the case of the
DRAM interface.
In other than DMAC signle address mode, burst access is possible when the DRAM space is
accessed.
Figure 7-31 shows the DACK output timing for the DRAM interface when DDS=0.
T_p
T_r
T_c1
T_c2
ø
A23 to A0
row
column
CSn (RAS)
CAS (UCAS)
LCAS (LCAS)
Read HWR (WE)
RCTS= 0
RCTS= 1
D15 to D0
CAS (UCAS)
LCAS (LCAS)
Write ^{HWR (WE)}
D15 to D0
DACK
Note: n = 2 to 5
Figure 7-31 DACK Output Timing when DDS=0 (Example Showing DRAM Access)
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