HD6432633 Datasheet, PDF (886/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and
generates the stop condition.
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
ICDRE
Generate start
condition
[5]
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W ^[7]
A
1
2
Bit 7 Bit 6
Data 1
IRIC
IRTR
Interrupt
request
Interrupt
request
ICDRT
Address + R/W
ICDRS
Address + R/W
Note: ICDR data
setting timing
Normal operation
Improper operation will
result.
User processing
[4] Write BBSY = 1
and SCP = 0
(generate start
condition)
[6] ICDR write
[6] IRIC clearance
Data 1
Data 1
[9] ICDR write
[9] IRIC clearance
Figure 18-8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)
SCL
(Master output)
89
SDA
(Master output)
Bit 0
Data 1 ^[7]
SDA
(Slave output)
A
ICDRE
IRIC
IRTR
ICDR
Data 1
1 234 5 67 89
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 2
[10]
A
Data 2
Generate start
condition
User processing
[9] ICDR write
[9] IRIC clearance
[11] ACKB read
[12] Write BBSY = 0
and SCP = 0
(generate stop
[12] IRIC clearance condition)
Figure 18-9 Example of Master Transmit Mode Stop Condition Generation Timing
(MLS = WAIT = 0)
832