HD6432633 Datasheet, PDF (1318/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

BCRH—Bus Control Register H
H'FED4
Bus Controller
Bit
:
Initial value :
R/W
:
7
ICIS1
1
R/W
6
5
4
3
2
1
0
ICIS0 BRSTRM BRSTS1 BRSTS0 RMTS2^*1 RMTS1^*1 RMTS0^*1
1
0
1
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Burst cycle select 1
0
Burst cycle = 1 state.
1
Burst cycle = 2 states.
Burst ROM enable
0
Area 0 is basic bus interface. (Initial value)
1
Area 0 is burst ROM interface.
Idle cycle insertion 0
0
No idle cycle is inserted when an external read cycle follows
an external write cycle.
1
An idle cycle is inserted when an external read cycle follows
an external write cycle. (Initial value)
Idle cycle insertion 1
0
No idle cycle is inserted when an external read cycle
follows an external read cycle of another area.
1
An idle cycle is inserted when an external read cycle
follows an external read cycle of another area. (Initial value)
Burst cycle select 0
0
Burst access = 4 words max.
1
Burst access = 8 words max.
RAM type select
RMTS2 RMTS1 RMTS0 Area 5
Area 4 Area 3
Area 2
0
0
0
Normal area
1
Normal area
DRAM area*
1
0
Normal area
DRAM area*
1
DRAM area*
1
1
1
Contiguous DRAM area*
Notes: When all areas selected in the DRAM area are set for 8-bit access, the PF2
pin can be used as an I/O port or BREQO or WAIT. When set for contiguous
DRAM the bus widths for areas 2 to 5 and the number of access states
(number of programmable waits) must be set to the same values. Do not
attempt to set combinations other than those shown in the table.
* This function is not available in the H8S/2695.
Note: *1 In the H8S/2695 only a 0 may be written to RMTS2, RMTS1, or RMTS0.
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