HD6432633 Datasheet, PDF (281/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Full access
T₁
T₂
Burst access
T₁
T₁
ø
Address bus
Low address only changes
CS0
AS
RD
Data bus
Read data
Read data Read data
Figure 7-32 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)
7.7.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.4.5, Wait
Control.
Wait states cannot be inserted in the burst cycle.
227