HD6432633 Datasheet, PDF (120/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

2.6 Instruction Set
2.6.1 Overview
The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2-1.
Table 2-1 Instruction Classification
Function
Instructions
Size Types
Data transfer
MOV
BWL 5
POP*¹, PUSH*¹
WL
LDM, STM
L
MOVFPE*³, MOVTPE*³
B
Arithmetic
operations
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
BWL 23
B
INC, DEC
BWL
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
BW
EXTU, EXTS
WL
TAS*⁴
B
MAC, LDMAC, STMAC, CLRMAC
—
Logic operations AND, OR, XOR, NOT
BWL 4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B
14
BIAND, BOR, BIOR, BXOR, BIXOR
Branch
Bcc*², JMP, BSR, JSR, RTS
—
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
9
Block data transfer EEPMOV
—
1
Notes: B-byte size; W-word size; L-longword size.
*1 POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
*2 Bcc is the general name for conditional branch instructions.
*3 Not available in the H8S/2633 Series.
*4 When using the TAS instruction, use register ER0, ER1, ER4, or ER5.
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