HD6432633 Datasheet, PDF (140/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

End of bus request
Bus request
Endroefqbu_B^ues_u^s_s^t _request
Program execution state
SLEEP
instruction
with
SSBY = 0
Bus-released state
Interrupt ^request
Sleep mode
SLEEP
instruction
with
SSBY = 1
Exception handling state
External interrupt request
Software standby mode
MRES= High
RES= High
STBY= High, RES= Low
Manual reset state *¹
Power-on reset state *¹
Hardware standby mode*²
Reset state *1
Power-down state*³
Notes: *1 From any state except hardware standby mode, a transition to the power-on reset state occurs whenever RES
goes low. From any state except hardware standby mode and power-on reset mode, a transition to the manual
reset state occurs whenever MRES goes low. A transition can also be made to the reset state when the
watchdog timer overflows.
*2 From any state, a transition to hardware standby mode occurs when STBY goes low.
*3 Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode.
See section 24, Power-Down States.
Figure 2-15 State Transitions
2.8.2 Reset State
The CPU enters the reset state when the RES pin goes low, or when the MRES pin goes low while
manual resets are enabled by the MRESE bit. In the reset state, currently executing processing is
halted and all interrupts are disabled.
For details of MRESE bit setting, see section 3.2.2, System Control Register (SYSCR).
Reset exception handling starts when the RES or MRES pin* changes from low to high.
The reset state can also be entered in the event of watchdog timer overflow. For details see section
15, Watchdog Timer.
Note: * MRES pin in the case of a manual reset.
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