HD6432633 Datasheet, PDF (179/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO)
Bit
:
7
6
5
4
3
2
1
0
—
IPR6 IPR5 IPR4
—
IPR2 IPR1 IPR0
Initial value :
0
1
1
1
0
1
1
1
R/W
:—
R/W R/W R/W
—
R/W
R/W
R/W
The IPR registers are thirteen 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5-3.
The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.
Table 5-3 Correspondence between Interrupt Sources and IPR Settings
Register
6 to 4
IPRA
IRQ0
IPRB
IRQ2
IRQ3
IPRC
IRQ6
IRQ7
IPRD
Watchdog timer 0
IPRE
PC break*
IPRF
TPU channel 0
IPRG
TPU channel 2
IPRH
TPU channel 4
IPRI
8-bit timer channel 0*
IPRJ
DMAC
IPRK
SCI channel 1
IPRL
8-bit timer 2, 3*
IPRO
SCI channel 3
Note: * This function is not available in the H8S/2695.
Bits
2 to 0
IRQ1
IRQ4
IRQ5
DTC*
Refresh timer
A/D converter, watchdog timer 1*
TPU channel 1
TPU channel 3
TPU channel 5
8-bit timer channel 1*
SCI channel 0
SCI channel 2
IIC (Option)*
SCI channel 4
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