HD6432633 Datasheet, PDF (1062/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

24.9.2 Exiting Sub-Sleep Mode
Sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or
IRQ0 to IRQ7), or signals at the RES, MRES, or STBY pins.
(1) Exiting Sub-Sleep Mode by Interrupts
When an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts.
In the case of IRQ0 to IRQ7 interrupts, sub-sleep mode is not cancelled if the corresponding
enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting
modules, the interrupt enable register has been set to disable the reception of that interrupt, or is
masked by the CPU.
(2) Exiting Sub-Sleep Mode by RES or MRES Pins
For exiting sub-sleep mode by the RES or MRES pins, see (2), Exiting Software Standby Mode by
RES or MRES pins in section 24.6.2, Exiting Software Standby Mode.
(3) Exiting Sub-Sleep Mode by STBY Pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.
24.10 Sub-Active Mode (This function is not available in the H8S/2695)
24.10.1 Sub-Active Mode
When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1,
LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to
sub-active mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1,
a transition is made to sub-active mode. And if an interrupt occurs in sub-sleep mode, a transition
is made to sub-active mode.
In sub-active mode, the CPU operates at low speed on the subclock, and the program is executed
step by step. Supporting modules other than TMR0 to TMR3, WDT0, and WDT1 are also
stopped.
When operating the CPU in sub-active mode, the SCKCR SCK2 to SCK0 bits must be set to 0.
24.10.2 Exiting Sub-Active Mode
Sub-active mode is exited by the SLEEP instruction or the RES, MRES, or STBY pins.
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