HD6432633 Datasheet, PDF (647/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 11-49 shows the timing in this case.
ø
Address
Write signal
Counter clear
signal
TCNT
TCNT write cycle
T1
T2
TCNT address
N
H'0000
Figure 11-49 Contention between TCNT Write and Clear Operations
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