HD6432633 Datasheet, PDF (1337/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

TCSR0—Timer Control/Status Register 0
H'FF74 (W), H'FF74 (R) WDT0
Bit
:7
6
5
4
OVF WT/IT TME
—
Initial value : 0
0
0
1
R/W
: R/(W)^* R/W
R/W
—
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W
R/W
R/W
Clock select 2 to 0
WDT0 input clock select
CKS2 CKS1 CKS0
Clock
Overflow cycle*
(when ø= 25MHz)
0
0
0
ø/2
20.4 µs
1
ø/64
652.8 µs
1
0
ø/128
1.3 ms
1
ø/512
5.2 ms
1
0
0
ø/2048
20.9 ms
1
ø/8192
83.6 ms
1
0
ø/32768
334.2 ms
1
ø/131072
1.34 s
Note: * The overflow cycle starts when TCNT starts counting
from H’00 and ends when an overflow occurs.
Timer enable
0 Initializes TCNT to H’00 and disables the counting operation.
1 TCNT performs counting operation.
Timer mode select
0
Interval timer mode: Interval timer interrupt (WOVI) request
sent to CPU when overflow occurs at TCNT.
1
Watchdog timer mode: WDTOVF signal output externally
when overflow occurs at TCNT. *
Note: * See section 15.2.3, Reset Control/Status Register (RSTCSR), for
details of when TCNT overflows in watchdog timer mode.
Overflow flag
0 [Clearing]
When 0 is written to OVF bit after reading TCSR when OVF=1.
1 [Setting]
When TCNT overflows (changes from H'FF to H'00).
When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset.
Notes: * Only 0 can be written to these bits (to clear these flags).
TCSR is write-protected by a password to prevent accidental overwriting.
For details see section 15.2.5, Notes on Register Access.
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