HD6432633 Datasheet, PDF (897/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

18.3.8 Operation Using the DTC*
The I²C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC* must be carried
out in conjunction with CPU processing by means of interrupts.
Table 18-5 shows some examples of processing using the DTC*. These examples assume that the
number of transfer data bytes is known in slave mode.
Note: * The DTC function is not available in the H8S/2695.
Table 18-5 Examples of Operation Using the DTC*
Item
Master Transmit Master Receive Slave Transmit Slave Receive
Mode
Mode
Mode
Mode
Slave address + Transmission by Transmission by
R/W bit
DTC* (ICDR write) CPU (ICDR write)
transmission/
reception
Reception by
CPU (ICDR read)
Reception by CPU
(ICDR read)
Dummy data —
Processing by
—
—
read
CPU (ICDR read)
Actual data
transmission/
reception
Transmission by Reception by
Transmission by Reception by DTC*
DTC* (ICDR write) DTC* (ICDR read) DTC* (ICDR write) (ICDR read)
Dummy data —
—
Processing by
—
(H'FF) write
DTC* (ICDR write)
Last frame
processing
Not necessary
Reception by
Not necessary
CPU (ICDR read)
Reception by CPU
(ICDR read)
Transfer request 1st time: Clearing Not necessary
processing after by CPU
last frame
processing
2nd time: End
condition issuance
by CPU
Automatic clearing Not necessary
on detection of end
condition during
transmission of
dummy data (H'FF)
Setting of
Transmission:
Reception: Actual
number of DTC* Actual data count data count
transfer data + 1 (+1 equivalent
frames
to slave address +
R/W bits)
Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Reception: Actual
data count
Note: * The DTC function is not available in the H8S/2695.
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