HD6432633 Datasheet, PDF (904/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Table 18-7 Permissible SCL Rise Time (t_Sr) Values
Time Indication
t_cyc
IICX Indication
I²C Bus
Specification ø =
(Max.)
5 MHz
ø=
8 MHz
ø= ø=
ø=
ø=
ø=
10 MHz 16 MHz 20 MHz 25 MHz 28 MHz
0
7.5t_cyc
Standard
mode
1000 ns
1000 ns 937 ns 750 ns 468 ns 375 ns 300 ns 267 ns
High-speed 300 ns
mode
300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns
1 17.5t_cyc
Standard
mode
1000 ns
1000 ns 1000 ns 1000 ns 1000 ns 875 ns 700 ns 624 ns
High-speed 300 ns
mode
300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns
• The I²C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I²C bus interface SCL and SDA output timing is prescribed by t_Scyc and t_cyc, as
shown in table 18-6. However, because of the rise and fall times, the I²C bus interface
specifications may not be satisfied at the maximum transfer rate. Table 18-8 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times.
t_BUFO fails to meet the I²C bus interface specifications at any frequency. The solution is either
(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of
a stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I²C bus.
t_SCLLO in high-speed mode and t_STASO in standard mode fail to satisfy the I²C bus interface
specifications for worst-case calculations of t_Sr/t_Sf. Possible solutions that should be
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I²C
bus.
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