HD6432633 Datasheet, PDF (284/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 7-35.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
ø
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
ø
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Long output
floating time
(a) Idle cycle not inserted
(ICIS1 = 0)
Data
collision
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 7-35 Relationship between Chip Select (CS) and Read (RD)
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