HD6432633 Datasheet, PDF (1353/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Appendix C I/O Port Block Diagrams
C.1 to C.12 are I/O port block diagrams for the H8S/2633, H8S/2632, H8S/2631, H8S/2633F, and
H8S/2633R. C.13 to C.24 are I/O port block diagrams for the H8S/2695.
C.1 Port 1 Block Diagram
P1n
*
Internal address bus
Reset
R
Q
D
P1nDDR
C
WDDR1
Reset
R
Q
D
P1nDR
C
WDR1
RDR1
System controller
Address output enable
PPG module
Pulse output enable
Pulse output
DMA controller
DMA transfer
acknowledge enable
DMA transfer acknowledge
TPU module
Output compare output/
PWM output enable
Output compare output/
PWM output
RPOR1
Input capture input
Legend
WDDR1 : Write to P1DDR
WDR1 : Write to P1DR
RDR1 : Read P1DR
RPOR1 : Read port 1
n= 0 or 1
Note: * Priority order: Address output > Output compare output/PWM output > DMA transfer acknowledge output >
pulse output > DR output
Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11)
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