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HD6432633 Datasheet, PDF (1204/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units) | |||
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A.4 Number of States Required for Instruction Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and
other cycles occurring in each instruction. Table A-4 indicates the number of states required for
each cycle. The number of states required for execution of an instruction can be calculated from
these two tables as follows:
Execution states = I Ã SI + J Ã SJ + K Ã SK + L ÃSL + M Ã SM + N Ã SN
Examples: Advanced mode, program code and stack located in external memory, on-chip
supporting modules accessed in two states with 8-bit bus width, external devices accessed in three
states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFC7:8
From table A-5:
I = L = 2, J = K = M = N = 0
From table A-4:
SI = 4, SL = 2
Number of states required for execution = 2 Ã 4 + 2 Ã 2 = 12
2. JSR @@30
From table A-5:
I = J = K = 2, L = M = N = 0
From table A-4:
SI = SJ = SK = 4
Number of states required for execution = 2 Ã 4 + 2 Ã 4 + 2 Ã 4 = 24
1150
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