HD6432633 Datasheet, PDF (154/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bit 5—BUZZ Output Enable (BUZZE)*: Disables/enables BUZZ output of PF1 pin. Input
clock of WDT1 selected by PSS, CKS2 to CKS0 bits is output as a BUZZ signal.
Bit 5
BUZZE
0
1
Description
Functions as PF1 input pin
Functions as BUZZ output pin
(Initial value)
Note: * This function is not available in the H8S/2695. This bit should not be set to 1.
Bit 4—LCAS Output Pin Selection Bit (LCASS)*: Selects the LCAS signal output pin.
Bit 4
LCASS
0
1
Description
Outputs LCAS signal from PF2
Outputs LCAS signal from PF6
(Initial value)
Note: * This function is not available in the H8S/2695. This bit should not be set to 1.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling
of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is
enabled for address output, the address is output regardless of the corresponding DDR setting.
When a pin is disabled for address output, it becomes an output port when the corresponding DDR
bit is set to 1.
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