HD6432633 Datasheet, PDF (209/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

6.1.3 Register Configuration
Table 6-1 shows the PC break controller registers.
Table 6-1 PC Break Controller Registers
Initial Value
Name
Abbreviation R/W
Power-On Manual
Reset
Reset
Break address register A
BARA
R/W H'XX000000 Retained
Break address register B
BARB
R/W H'XX000000 Retained
Break control register A
BCRA
R/(W)*² H'00
Retained
Break control register B
BCRB
R/(W)*² H'00
Retained
Module stop control register C MSTPCRC
R/W H'FF
Retained
Notes: *1 Lower 16 bits of the address.
*2 Only 0 can be written, for flag clearing.
Address*¹
H'FE00
H'FE04
H'FE08
H'FE09
H'FDEA
6.2 Register Descriptions
6.2.1 Break Address Register A (BARA)
Bit
: 31 • • • 24 23 22 21 20 19 18 17 16 • • • 7 6 5 4 3 2 1 0
— • • • — ^{BAA BAA BAA BAA BAA BAA BAA BAA} • • • ^{BAA BAA BAA BAA BAA BAA BAA BAA}
23 22 21 20 19 18 17 16
7 6 543 2 10
Initial value : _{Unde- • • • Unde- 0 0 0 0 0 0 0 0 • • • 0}
fined
fined
00
000
00
R/W
: — • • • — R/W R/W R/W R/W R/W R/W R/W R/W • • • R/W R/W R/W R/W R/W R/W R/W R/W
BARA is a 32-bit readable/writable register that specifies the channel A break address.
BAA23 to BAA0 are initialized to H'000000 by a power-on reset and in hardware standby mode.
Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified.
Bits 23 to 0—Break Address A23 to A0 (BAA23–BAA0): These bits hold the channel A PC
break address.
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