HD6432633 Datasheet, PDF (1295/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

TCR0—Timer Control Register 0
TCR3—Timer Control Register 3
H'FF10
H'FE80
Channel 0: TCR0
Channel 3: TCR3
Bit
:7
CCLR2
Initial value : 0
R/W
: R/W
6
5
4
3
CCLR1 CCLR0 CKEG1 CKEG0
0
0
0
0
R/W R/W R/W R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
TPU0
TPU3
Clock edge 1, 0
Time prescaler 2, 1, 0
TCR0
TPSC2 TPSC1 TPSC0
0
0
0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1
0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1
0
0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1
0 External clock: counts on TCLKC pin input
1 External clock: counts on TCLKD pin input
TCR3
TPSC2 TPSC1 TPSC0
0
0
0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
1
0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
1
0
0 External clock: counts on TCLKA pin input
1 Internal clock: counts on ø/1024
1
0 Internal clock: counts on ø/256
1 Internal clock: counts on ø/4096
CKEG1 CKEG0
0
0
Counts on rising edge.
1
Counts on falling edge.
1
—
Counts on both edges.
Note: Internal clock edge selection is valid only when the input clock is ø/4 or slower. This
setting is ignored when the input clock is ø/1 or an overflow or underflow in another
channel is selected.
Counter clear 2, 1, 0
CCLR2 CCLR1 CCLR0
0
0
0
TCNT clearing disabled.
1
TCNT cleared at TGRA compare match/input capture.
1
0
TCNT cleared at TGRB compare match/input capture.
1
TCNT cleared when other channel counters with synchronized
clearing or synchronized operation are cleared.*¹
1
0
0
TCNT clearing disabled.
1
TCNT cleared at TGRC compare match/input capture.*²
1
0
TCNT cleared at TGRD compare match/input capture.*²
1
TCNT cleared when other channel counters with synchronized
clearing or synchronized operation are cleared. *¹
Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
*2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer
register setting has priority, and compare match/input capture does not occur.
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