HD6432633 Datasheet, PDF (238/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Bit 5
RCDM
0
1
Description
DRAM interface: selects RAS up mode
DRAM interface: selects RAS down mode
(Initial value)
Bit 4—Reserved (CW2): Only write 0 to this bit.
Bits 3 and 2—Multiplex shift counts 1 and 0 (MXC1 and MXC0): These bits select the shift
amount to the low side of the row address of the multiplexed row/column address in DRAM
interface mode. They also select the row address to be compared in burst operation of the DRAM
interface.
Bit 3
MXC1
0
1
Bit 2
MXC0
0
1
0
1
Description
8-bit shift
(Initial value)
(1) 8-bit access space: target row addresses for comparison are A23 to A8
(2) 16-bit access space: target row addresses for comparison are A23 to A9
9-bit shift
(1) 8-bit access space: target row addresses for comparison are A23 to A9
(2) 16-bit access space: target row addresses for comparison are A23 to A10
10-bit shift
(1) 8-bit access space: target row addresses for comparison are A23 to A10
(2) 16-bit access space: target row addresses for comparison are A23 to A11
—
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1 and RLW0): These bits select the
number of wait states to be inserted in the CAS-before-RAS refresh cycle of the DRAM interface.
The selected number of wait states is applied to all areas set as DRAM space. Wait input via the
WAIT pin is disabled.
Bit 1
RLW1
0
1
Bit 0
RLW0
0
1
0
1
Description
Do not insert wait state
Insert 1 wait state
Insert 2 wait states
Insert 3 wait states
(Initial value)
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