HD6432633 Datasheet, PDF (264/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.5.7 Precharge State Control
When accessing DRAM, it is essential to secure a time for RAS precharging. In this LSI, it is
therefore necessary to insert 1 T_P state when accessing DRAM space. By setting the TPC bit of the
MCR to 1, T_P can be changed from 1 state to 2 states. Set the appropriate number of T_P cycles
according to the type of DRAM connected and the operation frequency of the LSI. Figure 7-16
shows the timing when T_P is set for 2 states.
Setting the TPC bit to 1 also sets the refresh cycle T_P to 2 states.
T_p1
T_p2
T_r
T_c1
T_c2
ø
A23 to A0
row
column
CSn (RAS)
CAS, LCAS
Read ^{HWR (WE)}
D15 to D0
RCTS= 0
RCTS= 1
CAS, LCAS
Write ^{HWR (WE)}
D15 to D0
Note: n= 2 to 5
Figure 7-16 Timing With Two Precharge Cycles
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