HD6432633 Datasheet, PDF (210/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

6.2.2 Break Address Register B (BARB)
BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3 Break Control Register A (BCRA)
Bit
:7
CMFA
Initial value : ₀
R/W
: R/(W)*
6
5
4
3
2
1
0
CDA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA
0
0
0
R/W R/W R/W
0
0
0
0
R/W R/W R/W R/W
Note: * Only 0 can be written, for flag clearing.
BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects
the break condition bus master, (2) specifies bits subject to address comparison masking, and (3)
specifies whether the break condition is applied to an instruction fetch or a data access. It also
contains a condition match flag.
BCRA is initialized to H'00 by a power-on reset and in hardware standby mode.
Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is
satisfied. This flag is not cleared to 0.
Bit 7
CMFA
0
1
Description
[Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
[Setting condition]
When a condition set for channel A is satisfied
(Initial value)
Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus
master.
Bit 6
CDA
0
1
Description
PC break is performed when CPU is bus master
PC break is performed when CPU or DTC is bus master
(Initial value)
156