HD6432633 Datasheet, PDF (875/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically
when the IRIC flag is cleared to 0.
Bit 5
IRTR
0
1
Description
Waiting for transfer, or transfer in progress
[Clearing conditions]
1. When 0 is written in IRTR after reading IRTR = 1
2. When the IRIC flag is cleared to 0
Continuous transfer state
[Setting conditions]
• In I²C bus interface slave mode
When the TDRE or RDRF flag is set to 1 when AASX = 1
• In other modes
When the TDRE or RDRF flag is set to 1
(Initial value)
Note: * The DTC function is not available in the H8S/2695.
Bit 4—Second Slave Address Recognition Flag (AASX): In I²C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in
SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 4
AASX
0
1
Description
Second slave address not recognized
(Initial value)
[Clearing conditions]
1. When 0 is written in AASX after reading AASX = 1
2. When a start condition is detected
3. In master mode
Second slave address recognized
[Setting condition]
When the second slave address is detected in slave receive mode and FSX = 0
Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The
I²C bus interface monitors the bus. When two or more master devices attempt to seize the bus at
nearly the same time, if the I²C bus interface detects data differing from the data it sent, it sets AL
to 1 to indicate that the bus has been taken by another master.
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