HD6432633 Datasheet, PDF (223/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Name
Wait
Symbol
WAIT
Bus request
BREQ
Bus request
acknowledge
BACK
Bus request output BREQO
I/O
Input
Input
Output
Output
Function
Wait request signal when accessing external 3-state
access space.
Request signal that releases bus to external device.
Acknowledge signal indicating that bus has been
released.
External bus request signal used when internal bus
master accesses external space when external bus is
released.
7.1.4 Register Configuration
Table 7-2 summarizes the registers of the bus controller.
Table 7-2 Bus Controller Registers
Initial Value
Name
Power-On
Abbreviation R/W Reset
Manual
Reset
Bus width control register
ABWCR
R/W H'FF/H'00*² Retained
Access state control register ASTCR
R/W H'FF
Retained
Wait control register H
WCRH
R/W H'FF
Retained
Wait control register L
WCRL
R/W H'FF
Retained
Bus control register H
BCRH
R/W H'D0
Retained
Bus control register L
BCRL
R/W H'08
Retained
Pin function control register
PFCR
R/W H'0D/H'00 Retained
Memory control register
MCR*³
R/W H'00
Retained
DRAM control register
DRAMCR*³ R/W H'00
Retained
Refresh timer counter
RTCNT*³
R/W H'00
Retained
Refresh time constant register RTCOR*³
R/W H'FF
Retained
Notes: *1 Lower 16 bits of the address.
*2 Determined by the MCU operating mode.
*3 This function is not available in the H8S/2695.
Address*¹
H'FED0
H'FED1
H'FED2
H'FED3
H'FED4
H'FED5
H'FDEB
H'FED6
H'FED7
H'FED8
H'FED9
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