HD6432633 Datasheet, PDF (237/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.2.7 Memory Control Register (MCR)*
Bit
:
Initial value :
R/W
:
7
TPC
0
R/W
6
5
4
3
2
1
0
BE RCDM CW2 MXC1 MXC0 RLW1 RLW0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The MCR is an 8-bit read/write register that, when areas 2 to 5 are set as the DRAM interface,
controls the DRAM strobe method, number of precharge cycles, access mode, address multiplex
shift amount, and number of wait states to be inserted when a refresh is performed.
The MCR is initialized to H'00 at a power-on reset and in hardware standby mode. It is not
initialized at a manual reset or in software standby mode.
Note: * This function is not available in the H8S/2695.
Bit 7—TP Cycle Control (TPC): When accessing areas 2 to 5, allocated to DRAM, this bit
selects whether the precharge cycle (T_P) is 1 state or 2 states.
Bit 7
TPC
0
1
Description
Insert 1 precharge cycle
Insert 2 precharge cycles
(Initial value)
Bit 6—Burst Access Enable (BE): This bit enables/disables burst access of areas 2 to 5, allocated
as DRAM space. DRAM space burst access is in high-speed page mode. When using EDO type in
this case, either select OE output or RAS up mode.
Bit 6
BE
0
1
Description
Burst disabled (always full access)
Access DRAM space in high-speed page mode
(Initial value)
Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are allocated to DRAM space, this bit
selects whether the RAS signal level remains Low while waiting for the next DRAM access (RAS
down mode) or the RAS signal level returns to High (RAS up mode), when DRAM access is
discontinued.
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