HD6432633 Datasheet, PDF (969/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

22.5.6 Flash Memory Power Control Register (FLPWCR)
Bit: 7
6
5
4
3
2
1
0
PDWND —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode.
Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory
power-down mode when the LSI switches to subactive mode.
Bit 7
PDWND
0
1
Description
Transition to flash memory power-down mode enabled
Transition to flash memory power-down mode disabled
(Initial value)
Bits 6 to 0—Reserved: These bits always read 0.
22.5.7 Serial Control Register X (SCRX)
Bit: 7
6
5
4
3
2
1
0
—
IICX1 IICX0 IICE FLSHE —
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
SCRX is an 8-bit readable/writable register that controls on-chip flash memory.
SCRX is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: This bit should always be written with 0.
Bits 6 and 5—I²C Transfer Rate Select (IICX1 and IICX0): These bits, together with bits
CKS2 to CKS0 in ICMR, select the transfer rate in master mode. For details of the transfer rate,
see section 18.2.4, I²C Bus Mode Register (ICMR).
Bit 4—I²C Master Enable (IICE): Controls access to the I²C bus interface data registers and
control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR). For details of the control, see
section 18.2.7, Serial Control Register X (SCRX).
915