HD6432633 Datasheet, PDF (1112/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

26.3.1 Clock Timing
Table 26-5 lists the clock timing
Table 26-5 Clock Timing
Condition:
PV_CC = 4.5 V to 5.5 V, AV_CC = 4.5 V to 5.5 V, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = PLLV_SS = 0 V, ø = 32.768 kHz, 2 to 28 MHz*,
T_a = –20°C to +75°C (regular specifications), T_a = –40°C to +85°C (wide-range
specifications)
28MHz
Item
Symbol Min
Max Unit
Test Conditions
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Clock oscillator settling
time at reset (crystal)
t _cyc
t _CH
t _CL
t _Cr
t _Cf
t _OSC1
35.7 500 ns
10
—
ns
10
—
ns
—
5
ns
—
5
ns
10
—
ms
Figure 26-2
Figure 26-3
Clock oscillator settling time in
software standby (crystal)
t _OSC2
5
—
ms
Figure 24-3
External clock output stabilization
delay time
t _DEXT
2
—
ms
Figure 26-3
32 kHz clock oscillation settling time
t _OSC3
—
2
s
Sub clock oscillator frequency
f _SUB
32.768 32.768 kHz
Sub clock (ø_SUB) cycle time
t _SUB
30.5 30.5 µs
Note: * The input clock frequency should be set to 25 MHz or less. If ø = 25 MHz to 28 MHz, use
the PLL to multiply the frequency (×2 or ×4).
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