HD6432633 Datasheet, PDF (1279/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

BCRA—Break Control Register A
BCRB—Break Control Register B
H'FE08
H'FE09
PBC
PBC
Bit
:
Initial value :
R/W
:
7
CMFA
0
R/(W)*
6
5
4
3
2
1
0
CDA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA
0
0
0
R/W R/W R/W
0
0
0
0
R/W R/W R/W R/W
CPU cycle/DTC cycle select A
0
When the CPU is the bus master, PC break performed.
1
When the CPU or DTC is the bus master, PC break performed.
Condition match flag A
0
[Clearing condition]
Writing 0 to CMFA after reading CMFA=1.
1
[Setting condition]
When channel A conditions are true.
Break address mask register A2 to A0
BAMRA
2
0
0
0
0
1
1
1
1
BAMRA
1
0
0
1
1
0
0
1
1
BAMRA
0
0
1
0
1
0
1
0
1
All bits, without masking BARA, included in break condition.
BAA0 (LSB) masked and not included in break condition.
BAA1 and BAA0 (low 2 bits) masked and not included in break condition.
BAA2 to BAA0 (low 3 bits) masked and not included in break condition.
BAA3 to BAA0 (low 4 bits) masked and not included in break condition.
BAA7 to BAA0 (low 8 bits) masked and not included in break condition.
BAA11 to BAA0 (low 12 bits) masked and not included in break condition.
BAA15 to BAA0 (low 16 bits) masked and not included in break condition.
Break condition select
CSELA1 CSELA0
0
0
0
1
1
0
1
1
Sets instruction fetch as break condition.
Sets data read cycle as break condition.
Sets data write cycle as break condition.
Sets data read/write cycle as break condition.
Notes: The bit configuration of BCRB is the same as that of BCRA.
* Only 0 can be written to these bits (to clear these flags).
Break interrupt enable
0
Disables PC break interrupt.
1
Enables PC break interrupt.
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