HD6432633 Datasheet, PDF (562/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

• Mode 7
PGDDR to 1 it becomes an output port, and by clearing it to 0 it becomes an input port.
Port G Data Register (PGDR)
Bit
:
7
6
5
4
—
—
— PG4DR
Initial value : Undefined Undefined Undefined 0
R/W
:—
—
—
R/W
3
PG3DR
0
R/W
2
PG2DR
0
R/W
1
0
PG1DR PG0DR
0
0
R/W
R/W
PGDR is an 8-bit read/write register and stores output data of port G output pins (PG4 to PG0).
Bits 7 to 5 are reserved bits. When the contents are read, undefined values are read. Write
processing is invalid.
In power-on reset or hardware standby mode, PGDR is initialized to H'00 (bits 4 to 0). In manual
reset or software standby mode, PGDR retains the last state.
(3) Port G Register (PORTG)
Bit
:
7
6
5
4
—
—
—
PG4
Initial value : Undefined Undefined Undefined —*
R/W
:—
—
—
R
Note: * Determined by the state of PG4 to PG0
3
PG3
—*
R
2
PG2
—*
R
1
PG1
—*
R
0
PG0
—*
R
PORTG is an 8-bit read only register and reflects the pin state. Write processing is invalid. Write
processing of output data of port G pins (PG4 to PG0) must be performed for PGDR.
Bits 7 to 5 are reserved bits. When the contents are read, undefined values are read. Write
processing is invalid.
If port G is read when PGDDR is set to 1, the value in PGDR is read. If port G is read when
PGDDR is cleared to 0, the pin state is read.
In power-on reset or hardware standby mode, port G is determined by the pin state because
PGDDR and PGDR are initialized. In manual reset or software standby mode, the last state is
retained.
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