HD6432633 Datasheet, PDF (905/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Table 18-8 I²C Bus Timing (with Maximum Influence of t_Sr/t_Sf)
Time Indication (at Maximum Transfer Rate) [ns]
Item
t_cyc
Indication
t_Sr/t_Sf
Influence
(Max.)
I²C Bus
Specifi-
cation ø =
(Min.) 5 MHz
ø=
8 MHz
ø= ø=
ø=
ø=
ø=
10 MHz 16 MHz 20 MHz 25 MHz 28 MHz
t_SCLHO
0.5t_SCLO
(–t_Sr)
Standard
mode
–1000
High-speed –300
mode
4000 4000 4000 4000 4000 4000 4000 4000
600
950
950
950
950
950
950
950
t_SCLLO
0.5t_SCLO
(–t_Sf )
Standard
mode
–250
High-speed –250
mode
4700 4750 4750 4750 4750 4750 4750 4750
1300 1000*¹ 1000*¹ 1000*¹ 1000*¹ 1000*¹ 1000*¹ 1000*¹
t_BUFO
0.5t_SCLO – 1t_cyc
( –t_Sr )
Standard
mode
–1000
High-speed –300
mode
4700 3800*¹ 3875*¹ 3900*¹ 3938*¹ 3950*¹ 3960*¹ 3964*¹
1300 750*¹ 825*¹ 850*¹ 888*¹ 900*¹ 910*¹ 912*¹
t_STAHO
0.5t_SCLO – 1t_cyc
(–t_Sf )
Standard
mode
–250
High-speed –250
mode
4000 4550 4625 4650 4688 4700 4710 4713
600
800
875
900
938
950
960
964
t_STASO
1t_SCLO
(–t_Sr )
Standard
mode
–1000
High-speed –300
mode
4700 9000 9000 9000 9000 9000 9000 9000
600
2200 2200 2200 2200 2200 2200 2200
t_STOSO
0.5t_SCLO + 2t_cyc
(–t_Sr )
Standard
mode
High-speed
mode
–1000
–300
4000 4400 4250 4200 4125 4100 4080 4071
600
1350 1200 1150 1075 1050 1030 1021
t_SDASO
1t_SCLLO*² – 3t_cyc Standard
–1000
250
3100 3325 3400 3513 3550 3580 3593
(master) (–t_Sr )
mode
High-speed –300
mode
100
400
625
700
813
850
880
893
t_SDASO
1t_SCLL*² – 3t_cyc*² Standard
–1000
250
3100 3325 3400 3513 3550 3580 3593
(slave) (–t_Sr )
mode
High-speed –300
mode
100
400
625
700
813
850
880
893
t_SDAHO
3t_cyc
Standard 0
mode
0
600
375
300
188
150
120
107
High-speed 0
mode
0
600
375
300
188
150
120
107
Notes: *1 Does not meet the I²C bus interface specification. Remedial action such as the following is necessary: (a) secure a
start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive
load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending
on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the I²C bus
interface specifications are met must be determined in accordance with the actual setting conditions.
*2 Calculated using the I²C bus specification values (standard mode: 4700 ns min.; high-speed mode: 1300 ns min.).
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