HD6432633 Datasheet, PDF (277/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.6 DMAC Single Address Mode and DRAM Interface
(This function is not available in the H8S/2695)
When burst mode is set for the DRAM interface, the DDS bit selects the output timing for the
DACK signal. It also selects whether or not to perform burst access when accessing the DRAM
space in DMAC single address mode.
7.6.1 DDS=1
Burst access is performed on the basis of the address only, regardless of the bus master. The
DACK output level changes to Low afer the T_c1 state in the case of the DRAM interface.
Figure 7-30 shows the DACK output timing for the DRAM interface when DDS=1.
T_p
T_r
T_c1
T_c2
ø
A23 to A0
row
column
CSn (RAS)
CAS (UCAS)
LCAS (LCAS)
Read HWR (WE)
RCTS= 0
RCTS= 1
D15 to D0
CAS (UCAS)
LCAS (LCAS)
Write ^{HWR (WE)}
D15 to D0
DACK
Note: n = 2 to 5
Figure 7-30 DACK Output Timing when DDS=1 (Example Showing DRAM Access)
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