HD6432633 Datasheet, PDF (645/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC* or DMAC* is activated, the flag is cleared automatically. Figure 11-46
shows the timing for status flag clearing by the CPU, and figure 11-47 shows the timing for status
flag clearing by the DTC* or DMAC*.
Note: * DMAC and DTC functions are not available in the H8S/2695.
TSR write cycle
T1
T2
ø
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 11-46 Timing for Status Flag Clearing by CPU
ø
Address
Status flag
Interrupt
request
signal
DTC^*/DMAC^*
read cycle
T1
T2
DTC^*/DMAC^*
write cycle
T1
T2
Source address
Destination
address
Note: * DMAC and DTC functions are not available in the H8S/2695.
Figure 11-47 Timing for Status Flag Clearing by DTC* or DMAC* Activation
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