HD6432633 Datasheet, PDF (1045/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

24.2.2 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
3
2
1
0
PSTOP —
—
— STCS SCK2 SCK1 SCK0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
—
—
—
R/W
R/W
R/W
R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control, selection of
operation when the PLL circuit frequency multiplication factor is changed, and medium-speed
mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls ø output. See section 24.12, ø Clock Output Disabling Function, for details.
Description
High-Speed Mode,
Bit 7 _{Medium-Speed Mode, Sleep Mode,}
Software Standby
Mode, Watch Mode*, Hardware Standby
PSTOP Sub-Active Mode* Sub-Sleep Mode* Direct Transition Mode
0
ø output (initial value) ø output
Fixed high
High impedance
1
Fixed high
Fixed high
Fixed high
High impedance
Note: * This function is not available in the H8S/2695.
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS
Description
0
Specified multiplication factor is valid after transition to software standby mode, watch
mode*, or subactive mode*
(Initial value)
1
Specified multiplication factor is valid immediately after STC bits are rewritten
Note: * This function is not available in the H8S/2695.
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