HD6432633 Datasheet, PDF (1013/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Section 23A Clock Pulse Generator
(H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
23A.1 Overview
The H8S/2633 Series has a built-in clock pulse generator (CPG) that generates the system clock
(ø), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock
oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL
circuit in the CPG. Frequency changes are performed by software by means of settings in the
system clock control register (SCKCR) and low-power control register (LPWRCR).
23A.1.1 Block Diagram
Figure 23A-1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
System
clock
oscillator
LPWRCR
STC1, STC0
PLL circuit
(×1, ×2, ×4)
ø SUB
Clock
selection
circuit
SCKCR
SCK2 to SCK0
Medium-
speed
clock divider
ø/2 to
ø/32
ø
Bus
master
clock
selection
circuit
OSC1
OSC2
Subclock
oscillator
Waveform
shaping
circuit
System clock Internal clock to
to ø pin supporting modules
WDT1 count clock
Legend:
LPWRCR: Low-power control register
SCKCR: System clock control register
Figure 23A-1 Block Diagram of Clock Pulse Generator
Bus master clock
to CPU, DMAC
and DTC
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