HD6432633 Datasheet, PDF (652/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 11-54 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
TGR write cycle
T1
T2
TGR address
M
M
Figure 11-54 Contention between TGR Write and Input Capture
598