HD6432633 Datasheet, PDF (252/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

16-Bit 2-State Access Space: Figures 7-8 to 7-10 show bus timings for a 16-bit 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states cannot be inserted.
Bus cycle
T₁
T₂
ø
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
LWR
D15 to D8
D7 to D0
Note: n = 0 to 7
High
Valid
High impedance
Figure 7-8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
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