HD6432633 Datasheet, PDF (1052/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 24-2 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode
ø,
supporting module clock
Bus master clock
Internal address bus
SBYCR
SBYCR
Internal write signal
Figure 24-2 Medium-Speed Mode Transition and Clearance Timing
24.4 Sleep Mode
24.4.1 Sleep Mode
When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR
LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU’s internal registers are retained. Other supporting modules do not stop.
24.4.2 Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES, MRES, or STBY pins.
(1) Exiting Sleep Mode by Interrupts
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
(2) Exiting Sleep Mode by RES or MRES Pins
Setting the RES or MRES pin level Low selects the reset state. After the stipulated reset input
duration, driving the RES and MRES pins High starts the CPU performing reset exception
processing.
(3) Exiting Sleep Mode by STBY Pin
998