HD6432633 Datasheet, PDF (290/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

7.10.4 Transition Timing
Figure 7-39 shows the timing for transition to the bus-released state.
ø
Address bus
Data bus
CSn
AS
RD
HWR, LWR
CPU cycle
T₀
T₁
T₂
Address
External bus released state
CPU
cycle
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
BREQ
BACK
BREQO*
Minimum
1 state
[1]
[2]
[3]
[4]
[5]
[6]
[1] Low level of BREQ pin is sampled at rise of T₂ state.
[2] BACK pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
[3] BREQ pin state is still sampled in external bus released state.
[4] High level of BREQ pin is sampled.
[5] BACK pin is driven high, ending bus release cycle.
[6] BREQO signal goes high 1.5 clocks after BACK signal goes high.
Note: * Output only when BREQOE is set to 1.
Figure 7-39 Bus-Released State Transition Timing
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