HD6432633 Datasheet, PDF (854/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

• Wait function in master mode (I²C bus format)
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
• Wait function in slave mode (I²C bus format)
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interrupt sources
 Data transfer end (including transmission mode transition with I²C bus format and address
reception after loss of master arbitration)
 Address match: when any slave address matches or the general call address is received in
slave receive mode (I²C bus format)
 Stop condition detection
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (with SCL and SDA pins)
 Two pins—P35/SCL0 and P34/SDA0—(normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
 Two pins—P33/SCL1 and P32/SDA1—(normally CMOS pins) function as NMOS-only
outputs when the bus drive function is selected.
18.1.2 Block Diagram
Figure 18-1 shows a block diagram of the I²C bus interface.
Figure 18-2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins are
NMOS open drains, and it is possible to apply voltages in excess of the power supply (PV_CC)
voltage for this LSI. Set the upper limit of voltage applied to the power supply (PV_CC) power
supply range + 0.3 V, i.e. 5.8 V. Channel 1 I/O pins are driven solely by NMOS, so in terms of
appearance they carry out the same operations as an NMOS open drain. However, the voltage
which can be applied to the I/O pins depends on the voltage of the power supply (PV_CC) of this
LSI.
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