HD6432633 Datasheet, PDF (36/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

6.3 Operation .......................................................................................................................... 159
6.3.1 PC Break Interrupt Due to Instruction Fetch....................................................... 159
6.3.2 PC Break Interrupt Due to Data Access .............................................................. 159
6.3.3 Notes on PC Break Interrupt Handling ............................................................... 160
6.3.4 Operation in Transitions to Power-Down Modes ............................................... 160
6.3.5 PC Break Operation in Continuous Data Transfer .............................................. 161
6.3.6 When Instruction Execution is Delayed by One State ........................................ 162
6.3.7 Additional Notes ................................................................................................. 163
Section 7 Bus Controller................................................................................................. 165
7.1 Overview........................................................................................................................... 165
7.1.1 Features ............................................................................................................... 165
7.1.2 Block Diagram..................................................................................................... 167
7.1.3 Pin Configuration ................................................................................................ 168
7.1.4 Register Configuration ........................................................................................ 169
7.2 Register Descriptions........................................................................................................ 170
7.2.1 Bus Width Control Register (ABWCR) .............................................................. 170
7.2.2 Access State Control Register (ASTCR)............................................................. 171
7.2.3 Wait Control Registers H and L (WCRH, WCRL)............................................. 172
7.2.4 Bus Control Register H (BCRH)......................................................................... 175
7.2.5 Bus Control Register L (BCRL).......................................................................... 178
7.2.6 Pin Function Control Register (PFCR) ............................................................... 180
7.2.7 Memory Control Register (MCR) ....................................................................... 183
7.2.8 DRAM Control Register (DRAMCR)................................................................. 185
7.2.9 Refresh Timer Counter (RTCNT) ....................................................................... 187
7.2.10 Refresh Time Constant Register (RTCOR)......................................................... 187
7.3 Overview of Bus Control.................................................................................................. 188
7.3.1 Area Partitioning ................................................................................................. 188
7.3.2 Bus Specifications ............................................................................................... 189
7.3.3 Memory Interfaces............................................................................................... 190
7.3.4 Interface Specifications for Each Area................................................................ 191
7.3.5 Chip Select Signals.............................................................................................. 192
7.4 Basic Bus Interface........................................................................................................... 193
7.4.1 Overview ............................................................................................................. 193
7.4.2 Data Size and Data Alignment ............................................................................ 193
7.4.3 Valid Strobes ....................................................................................................... 195
7.4.4 Basic Timing ....................................................................................................... 196
7.4.5 Wait Control ........................................................................................................ 204
7.5 DRAM Interface
(This function is not available in the H8S/2695).............................................................. 206
7.5.1 Overview ............................................................................................................. 206
7.5.2 Setting up DRAM Space ..................................................................................... 206
7.5.3 Address Multiplexing .......................................................................................... 207
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