HD6432633 Datasheet, PDF (1061/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

24.8.3 Notes
(1) I/O Port Status
The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the
address bus and bus control signals continue to be output. Therefore, when a High level is output,
the current consumption is not diminished by the amount of current to support the High level
output.
(2) Current Consumption when Waiting for Oscillation Stabilization
The current consumption increases during stabilization of oscillation.
(3) DMAC/DTC activation and sub-active mode/watch mode transition
When a transition is made to sub-active mode or watch mode, make a module stop setting for the
DMAC/DTC (write 1 to the corresponding bit in MSTPCR), then read 1 from that bit for
confirmation, before making the mode transition.
When exiting the module stop state (by writing 0 to the corresponding bit in MSTPCR), first make
a transition from sub-active mode to active mode.
If a DMAC/DTC activation source occurs in sub-active mode, the DMAC/DTC is activated when
the module stop state is exited after a transition is made to active mode.
(4) Interrupt sources and sub-active mode/watch mode transition
For on-chip peripheral modules that stop operating in sub-active mode (DMAC, DTC, TPU, FRT,
TMRX, TMRY, timer connection, I²C), a corresponding interrupt cannot be cleared in sub-active
mode. Therefore, CPU interrupt source clearance cannot be effected if a transition is made to sub-
active mode when an interrupt has been requested.
Interrupts for these modules should be disabled before executing a SLEEP instruction and making
a transition to sub-active mode or watch mode.
24.9 Sub-Sleep Mode (This function is not available in the H8S/2695)
24.9.1 Sub-Sleep Mode
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode.
In sub-sleep mode, the CPU is stopped. Supporting modules other than TMR0 to TMR3, WDT0,
and WDT1 are also stopped. The contents of the CPU’s internal registers, the data in internal
RAM, and the statuses of the internal supporting modules (excluding the SCI, ADC, and 14-bit
PWM) and I/O ports are retained.
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