HD6432633 Datasheet, PDF (928/1453 Pages) Renesas Technology Corp – Series of Microcomputers (MCUs: microcomputer units)

19.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit is set to 1, then starts conversion. Figure 19-5 shows the A/D
conversion timing. Table 19-4 indicates the A/D conversion time.
As indicated in figure 19-5, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 19-4.
In scan mode, the values given in table 19-4 apply to the first conversion time. The values given
in table 19-5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and
CKS0 in ADCR to give a conversion time of at least 10 µs when AV_CC ≥ 4.5 V, and at least 16 µs
when AV_CC < 4.5 V.
(1)
ø
Address
(2)
Write signal
Input sampling
timing
ADF
t_D
t_SPL
t _CONV
Legend
(1) : ADCSR write cycle
(2) : ADCSR address
t_D
: A/D conversion start delay
t_SPL : Input sampling time
t_CONV : A/D conversion time
Figure 19-5 A/D Conversion Timing
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